The Test Engineer will develop and debug test programs for Sidense Logic NVM (OTP) memories and other hard macros. He/she will be responsible for all aspects of evaluation, characterization and reliability testing.
-Create and execute test plans for evaluation, characterization and qualification of test chips.
-Create and debug Credence PK2 tester programs for new OTP architectures in advanced process nodes (45/40/28nm); learn and maintain tester programs for existing test chips (180-55nm).
-Develop programming algorithms that optimize programming time and yield.
-Investigate functional and reliability issues, drive performance issues to root cause.
-Interface with Sidense design and application engineers, customers and fabs on product/test issues.
-Minimum 5 years hands-on experience in product/test engineering.
-Experience in evaluating and characterizing semiconductor memory.
-Experience creating test plans and programs, analyzing test data and presenting results, and writing test reports.
-Experience in memory ATE programming (ex. Credence Kalos) and tester operation.
-Experience with semiconductor parametric/yield databases and statistical analysis tools.
-Experience with programming languages (C, Java, Perl).
Bachelors or Masters degree in Electrical Engineering (preferred), Computer Engineering or Computer Science