Sidense provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required and no impact on product yield. The Company’s innovative one-transistor 1T-Fuse™ architecture provides the industry’s smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (NVM) IP solution. With over 70 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.
Sidense OTP memory, embedded in over 100 customer designs, is available from 180nm down to 40nm and is scalable to 28nm and below. The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic.
Sidense is headquartered in Ottawa, Ontario and services an expanding worldwide customer base.
- Silicon Valley, California (Santa Clara); or
- Ottawa, Ontario
The Senior Test Engineer will develop and debug test programs for Sidense Logic NVM (OTP) memories and other hard macros. He/she will be responsible for all aspects of evaluation, characterization and reliability testing.
- Create and execute test plans for evaluation, characterization and qualification of test chips.
- Create and debug Credence PK2 tester programs for new OTP architectures in advanced process nodes (45/40/28nm); learn and maintain tester programs for existing test chips (180-55nm).
- Develop programming algorithms that optimize programming time and yield.
- Investigate functional and reliability issues, drive performance issues to root cause.
- Interface with Sidense design and application engineers, customers and fabs on product/test issues.
- Bachelors or Masters’ degree in Electrical Engineering (preferred), Computer Engineering or Computer Science
- Minimum 10 years hands-on experience in product/test engineering.
- Experience in evaluating and characterizing semiconductor memory.
- Experience creating test plans and programs, analyzing test data and presenting results, and writing test reports.
- Experience in memory ATE programming (ex. Credence Kalos) and tester operation.
- Experience with semiconductor parametric/yield databases and statistical analysis tools.
- Experience with programming languages (C, Java, Perl).
- Ability to work with minimal supervision and interface effectively with remote teams
Email your cover letter and resume in confidence to hr[at]sidense.com specifying the title of the position you are applying for in the subject line of your message. Please be sure to provide some insight into your initiative, skills and achievements.