Sidense provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps. The Company's innovative one-transistor 1T-Fuse™ architecture provides the industry's smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (NVM) IP solution. With over 70 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.
Sidense OTP memory, embedded in over 100 customer designs, is available from 180nm down to 40nm and is scalable to 28nm and below. The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic.
This newly created role of Director of Research and Development will work directly with the Chief Technology Officer to lead new product definition and implementation for Sidense. The Director of R&D will be a key contributor to the Company roadmap by proposing and evaluating new and improved product concepts and applications. The Director will lead a dedicated Research and Development team developing novel embedded NVM Memory IP products from concept to volume production in the most advanced process nodes. The R&D team will work on OTP memory design, including device engineering, layout and circuit design, hardware design and memory compiler development.
-Masters degree in Electrical Engineering
-10 years design experience with memory IP development including product specification, layout, circuit and logic design, as well as product testing and qualification.
Leadership and Management Skills Requirements:
-Experience in leading memory or mixed signal product definition and specifications
-Highly organized and experienced in design checkpoint methodology
-Strong writing and presentation skills
-Ability to lead, motivate and coach innovative solutions
-Experience dealing with foundries, contractors and customers
-Experience in memory or analog IP feasibility study including performance, power, layout and yield estimates inadvanced process nodes
-Ability to assist in product development
-Track record showing ability to innovate and implement novel solutions
-Experience in design audits and reviews
Essential Product and Design Skills:
-Memory Compiler Project Lead with strong focus on SOC memory application collateral
-Experience in memory macrocell design, circuit topologies for small and large arrays
-Experience with analog circuits including voltage references, internal voltage regulators, charge pumps and power-up circuits
-Experience with standard cells development
-Basic logic design skills (FFs, timers, counters, decoders, control logic, state machines)
-Experience with OTP and/or NVM design, testing and reliability
-Basic understanding of digital design flow as it relates to logic verification, static timing analysis, margin for statistical phenomena in digital and memory designs at advanced technology nodes, power sensitivity to designchoices and layout integration
-Basic understanding of device physics
-Basic understanding of advanced process technologies
-Experience with device operation beyond foundry specified voltage range and specs
-Good understanding of custom IC CAD tools including hands on tapeout experience
-IC Testing and Product debugging, performance and yield optimization
-Good understanding of device characteristics and familiarity with test lab equipment
-Experience with IC product reliability and qualification