The candidate must have a minimum of 8 years of experience in FPGA or ASIC development which must include both design and verification. The candidate will work within a team responsible for the development of OTN Intellectual Property (IP) with the responsibility of both RTL design and verification.
- Work within a team of engineers to deliver standards compliant IP blocks for use in OTN FPGAs or ASICs.
- Develop and document the design using Verilog
- Develop and document the verification environment using SystemVerilog + UVM
- Develop and execute individual test-cases against the RTL
- Issue and track bug reports from inception to closure
- Mentor junior engineers
Must comprehensively possess the following skills
- Telecommunications Protocol knowledge (OTN, Sonet, Ethernet, etc)
- FPGA compilation tools
- Randomised and Directed Verification Methodologies
- Unix/Linux Shell scripting
- Source code revisioning systems, SVN, CVS, RCS e.g.
- Demonstrated Verbal and written communications skills
- Ability to mentor junior engineers
- Ability to independently execute on a project while working well with others in the group
Useful knowledge to have
- OTN transport systems
- Debugging Tools
- PERL, TCL, and C/C++ programming
Education and Experience
- MSEE with 8 years of experience or BSEE with 9 years of experience in ASIC or FPGA development
Note: Only selected candidates will be contacted.