Apply here; http://ch.tbe.taleo.net/CH18/ats/careers/requisition.jsp?org=HUAWEICA&cws=1&rid=255
The Canada R&D Centre, based in Ottawa, is a leading research and development center for high end, fully programmable, packet processors and SOC.
In this role, you will be responsible for all aspects of physical designs within a COT flow.
This includes early involvement analyzing architecture impact on possible physical implantations all the way to placement, CTS, routing, timing closure, physical verification and power integrity signoff for block level and chip level.
You will work with architecture and silicon design teams to drive the design and optimization of the state-of-the-art ASIC. You must be self-motivated and able to work independently, but thrive in a team-based environment. You will work closely with the R&D teams based in other overseas centers as well as at Huawei Headquarters in China.
Key qualifications must include:
-5+ years of COT physical design experience, 28nm experience a bonus
-Hands on experience with all aspects of large scale SoC, from floor planning to final GDS delivery to commercial foundries, meeting product and foundry requirements
-Analytical problem solving skills to debug clock tree and timing closure
-Should be familiar with extraction, signal integrity and static timing analysis. Clock tree synthesis and routing is a must
-Hierarchical layout methodology
-Power island implementation
-Good team work spirit and adaptability
-Strong communication skills to interact with geographically dispersed ASIC teams
-Experience in adapting flow to new tools and technologies
-Thrive in a dynamic, innovative and research oriented environment
-Good Knowledge and experience on related PD tools such as ICC, Encounter, Redhawk,PT-SI, PT-PX, Calibre